71M6533/G/H and 71M6534/H Data Sheet
FDS_6533_6534_004
Interrupt Enable
Name Location
Interrupt Flag
Name Location
Interrupt Description
AUTOWAKE flag
EX_XFER
EX_RTC
IEN_WD_NROVF
IEN_SPI
EX_FWCOL
EX_PLL
2002[0]
2002[1]
20B0[0]
20B0[4]
2007[4]
2007[5]
IE_XFER
IE_RTC
WD_NROVF_FLAG
SPI_FLAG
IE_FWCOL0
IE_FWCOL1
IE_PLLRISE
IE_PLLFALL
IE_WAKE
IE_PB
SFR E8[0]
SFR E8[1]
20B1[0]
20B1[4]
SFR E8[3]
SFR E8[2]
SFRE8[6]
SFRE8[7]
SFRE8[5]
SFRE8[4]
XFER_BUSY interrupt (INT 6)
RTC_1SEC interrupt (INT 6)
WDT near overflow (INT 6)
SPI Interface (INT2)
FWCOL0 interrupt (INT 2)
FWCOL1 interrupt (INT 2)
PLL_OK rise interrupt (INT 4)
PLL_OK fall interrupt (INT 4)
?
PB flag ?
The AUTOWAKE and PB flag bits are shown in Table 31 because they behave similarly to interrupt flags,
?
even though they are not actually related to an interrupt. These bits are set by hardware when the MPU
wakes from a push button or wake timeout. The bits are reset by writing a zero. Note that the PB flag is
set whenever the PB is pushed, even if the part is already awake.
WD_NROVF_FLAG is set approximately 1 ms before a WDT reset occurs. The flag can be cleared by
writing a zero to it and is automatically cleared by the falling edge of WAKE.
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 32 :
Table 32: Interrupt Priority Level Groups
Group Members
0
1
2
3
4
5
External interrupt 0, Serial
channel 1 interrupt
Timer 0 interrupt, External
interrupt 2
External interrupt 1, External
interrupt 3
Timer 1 interrupt, External
interrupt 4
Serial channel 0 interrupt,
External interrupt 5
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table33) bysettingorclearingonebitintheSFRinterruptpriorityregister IP0 andonein IP1 (Table34).
If requests of the same priority level are received simultaneously, an internal polling sequence as shown
in Table 35 determines which request is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 33: Interrupt Priority Levels
34
IP1 [x]
0
0
1
1
IP0 [x]
0
1
0
1
Priority Level
Level 0 (lowest)
Level 1
Level 2
Level 3 (highest)
Rev 2
相关PDF资料
71M6541F-DB DEMO BOARD 71M6541F
71M6543F-DB-CT DEMO BOARD 71M6543F-DB-CT
72-CNV-5 CONVERTER RS-232 TO RS-422 5V
72346-001 72346-1-SCA-II REC
72347-001LF CONN RECEPT SCA2 20POS VERT PCB
72436-001LF 80POS EXT HT. REC SCA-2
72442-201LF CONN RECEPT SCA2 80POS VERT PCB
72512-001 5 X 12 COVERS
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